Positron AI Raises $875M for Inference Chips That Replace HBM Memory

By Carlos Montiel | Enterprise AI Specialist
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Published: 2026-09-13 | By: Carlos Montiel | Reading time: ~5 minutes

Positron AI closed a $875 million Series C round at a $5 billion valuation — five times what it was worth in February — betting that swapping out HBM memory for smartphone-grade LPDDR5X can solve inference's real bottleneck: not compute, but memory.

The bet: memory before raw compute

The round, co-led by NEA, Atreides Management, Valor Equity Partners, Andra Capital, Dylan Patel's SemiAnalysis Capital, and Jim Clark (co-founder of Silicon Graphics and Netscape), will fund the tapeout of its Asimov chip, bringing its Titan system into production, and a 2+ MW engineering data center. Positron's thesis is simple to state and hard to execute: in large-model inference, the bottleneck isn't how much a chip can compute, but how much memory it has available and how fast it can read it. That's why its Asimov chip pairs a systolic array architecture with co-located memory that holds the model's weights directly, instead of relying on HBM (high-bandwidth memory) — the standard used by Nvidia and AMD that's currently scarce and expensive due to AI boom demand.

LPDDR5X: phone memory for 32-trillion-parameter models

Instead of HBM, Asimov uses LPDDR5X — the same type of memory found in high-end smartphones — which is cheaper and doesn't compete for the same strained supply chain. Positron claims its systems reach more than 90% utilization of LPDDR5X bandwidth, compared to a typical 30% HBM utilization in competing accelerators. The Titan system can scale to 18.4 terabytes of LPDDR5X memory with 23.68 terabits per second of bandwidth, combining up to 8 Asimov chips per unit and enabling clusters of up to 16,384 accelerators — enough, the company says, for models with up to 32 trillion parameters and context windows of 10 billion tokens.

The announcement, in numbers: - Series C round: $875 million - Valuation: $5 billion (5x since February 2026) - Asimov chip: tapeout expected late 2026 on TSMC's N3P process - Titan system: volume production expected in the second half of 2027 - Company claim: up to 26x more tokens per dollar than an Nvidia Blackwell GB300 NVL72 (based on internal simulations)

CEO Mitesh Agrawal summed up the company's priority after closing the round: "our focus now is getting Asimov's tapeout done, bringing Titan to production, and scaling manufacturing to meet the demand in front of us." It's worth noting the 26x tokens-per-dollar figure comes from Positron's own internal simulations, not independently published benchmarks — normal for this pre-production stage, but worth treating as a projection rather than a verified fact until there's physical hardware running real workloads.

What this means for a company that buys or uses AI: if Positron hits its timeline (tapeout by late 2026, production in the second half of 2027), the enterprise inference market could stop depending exclusively on the availability — and price — of HBM-equipped GPUs. For companies in Guatemala and Latin America currently paying inflated API rates or infrastructure costs due to HBM scarcity, a viable alternative based on mass-market memory could translate, by 2027-2028, into lower inference costs and less dependence on a single hardware vendor. For now, it remains a venture bet on a technical thesis not yet proven in production at scale.

An increasingly crowded inference chip market

Positron isn't alone in this thesis: the round arrives amid record investment in specialized inference silicon, with startups like Etched raising hundreds of millions for chips designed specifically to serve frontier models. What sets Positron apart is that it's explicitly betting on avoiding HBM memory rather than competing for it — which, if the technical execution delivers as the company promises, could differentiate it in a market where almost every other player is constrained by the same scarce supply chain.

Carlos Montiel
Enterprise AI Solutions Architect
LLM, Agent, and Orchestration Specialist
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